ASIC III - AMZ27336.4

Saved job description

Employer: Annapurna Labs (U.S.) Inc.

Position: ASIC III - AMZ27336.4

Location: Austin, TX

Multiple Positions Available:

Engage in definition, design and validation of AWS next generation ML Chips, Cards and server integration. • Participate in the design and execution of all HBM, Memories and Serdes topics, with the goal of creating and customized platforms that fit within AWS datacenter’s world leading technology. • Work with vendors, understand the settings, write/modify tests, debug and collect data in the fleet • Participate in the code review process, design discussions, team planning, and ticket/metric/COE reviews • Collaborate with architects, design teams, software engineers to deliver the next generation ML chip. • Responsible for IP integration, 2.5D design, bring up, Characterization and validation. • Focus on operational excellence, constructively identifying problems and proposing solutions.

(40 hours / week, 8:00am-5:00pm, Salary Range $202779 - $215300)

Amazon.com is an Equal Opportunity – Affirmative Action Employer – Minority / Female / Disability / Veteran / Gender Identity / Sexual Orientation

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Requirements: A Master’s degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering, or a related field and 5 years of experience in the job offered or a related

occupation. In the alternative, a Bachelor’s degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering or a related field followed by 7 years of

progressively responsible post-baccalaureate experience in the job offered or a related occupation.

Must have 3 years of experience in the following:

1) SOC/IO/Subsystems.

2) DDR/HBM at the PHY and controller level and DDR/HBM training, timing parameters and/or controller features.

3) Driving the IP Integration and designing silicon and 2.5D packaging.

4) Supporting the physical design team, reviewing clocking and timing constraints

5) Driving cross-functional triage effort on complex functional and performance issues.

6) Taking the leadership role in post-silicon bring-up of IO and HBM/DRRx stack.

7) Defining boot-up initialization, reset flow, training sequence.

8) Performing system-level debug and root-cause analysis through bringup, characterization, validation and production phase.

9) Working with 3rd party IP and memory vendors

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