Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning

Saved job description

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost.

You’ll provide leadership in the application of new technologies to large scale deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought-leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Key job responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis

• Write, debug & validate timing constraints for blocks and full-chip.

• Run Static Timing Analysis and give frequent feedback to team members and leads.

• Provide guidance on how to fix timing issues (generate ECOs, fix constraint issues).

• Develop scripts to automate running timing analysis and generate reports.

• Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

Requirements: - Experience scripting or coding

- BS + 6yrs or MS + 4yrs or PhD + 2yr in EE/CS

- Expertise in timing analysis fundamentals

- 1+ years doing Static Timing Analysis

- 1+ years with timing constraint development

- Timing Analysis using EDA tools (examples: PrimeTime, Tempus, or others)

- Understanding of ASIC Physical Design from RTL-to-GDSII

- Understanding of other sign-off activities (ir/em, physical verification, DFT)

- 1+ years of scripting experience with Tcl, Perl or Python