Mgr III, ASIC - AMZ25936.5

Saved job description

Employer: Annapurna Labs (U.S.) Inc.

Position: Mgr III, ASIC - AMZ25936.5

Location: Cupertino, CA

Multiple Positions Available:

1. Lead a team of verification engineers in the functional verification of advanced AI-focused System-on-Chip (SoC) designs, including neural network accelerators, high-speed interconnects, and memory subsystems.

2. Manage project schedules, deliverables, and performance metrics while mentoring and developing junior engineers.

3. Define, develop, and implement comprehensive verification strategies and testplans aligned with AI-specific architectural and performance goals.

4. Oversee creation of modular, reusable UVM(Universal Verification Methodology) based testbenches for verifying components such as compute engines, DMA controllers, and AI-specific processing blocks.

5. Collaborate closely with architecture, RTL design, software, and machine learning teams to ensure full coverage of functional requirements and performance metrics.

6. Drive verification closure through coverage-driven verification methodologies, including code, functional, and assertion coverage.

7. Utilize simulation tools, formal verification techniques, and emulation platforms to validate complex AI workloads and edge-case scenarios.

(40 hours / week, 8:00am-5:00pm, Salary Range $223641 - $272400)

Amazon.com is an Equal Opportunity – Affirmative Action Employer – Minority / Female / Disability / Veteran / Gender Identity / Sexual Orientation

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Requirements: A Master’s degree or foreign equivalent in Computer Science, Computer Engineering or related field and 5 year(s) of experience in the job offered or a related occupation. In the alternative,

a Bachelor’s degree or foreign equivalent in Computer Science, Computer Engineering or related field followed by 8 year(s) of progressively responsible experience in the job offered or a

related occupation.

Must have 5 year(s) of experience in the following:

• Design verification using System Verilog and UVM.

• Testbench development including: testplans, stimulus, checkers, assertions and coverage.

• Verify and integrate multiple levels of design including: custom chip blocks, 3rd party IPs and VIPs, sub-systems, and fullchip SOC systems.

The pay range for this position in Cupertino, CA is $223641 - $272400 (yr); however, base pay offered may vary depending on job-related knowledge, skills, and experience. A sign-on bonus and restricted stock units may be provided as part of the compensation package, in addition to a full range of medical, financial, and/or other benefits, dependent on the position offered. This information is provided by California Equal Pay Act. Base pay information is based on market location. Applicants should apply via Amazon's internal or external careers site.

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