Sr. Engineer, Silicon Validation , Annapurna Labs

Saved job description

As a Sr ASIC validation engineer on our team, you will independently lead the SW driven early stages test development for our Trainium and Inferentia AI acceleration engines , drive the testing strategy at the sub system/ system level, drive functional and performance pre silicon verification and ensure silicon quality. You will tackle complex problems rooted across hardware and software domains, develop innovative validation methodologies, and set the standard for engineering excellence across our organization.

This role requires a unique combination of deep technical expertise in in HW/SW concurrent verification methodologies and strategies as well as excellent knowledge and understanding of our AI acceleration engines architecture and design. The role requires coordination across teams, and the ability to navigate ambiguity during silicon development cycles. You will mentor junior and senior engineers, influence architectural decisions that impact multiple chip generations, and ensure our custom silicon meets the highest standards of quality and reliability.

Key job responsibilities

- Develop, run and debug SW based testing primarily for the pre silicon validation of the compute and AI acceleration engines

- Develop unit testing as well as end to end testing, varying simple single engine operations as well as entire neural network layers.

- Focus on early development of testing, finding early bugs and supporting quick ramp of fully compiled software (aka Neuron) testing on emulation

- Contribute and debug over multiple layers of the stack for test development – from RTL through firmware, software and testbench development

- Re-use and scale verification infra across pre-Si and emulation teams.

- Closely collaborate with Architects, Chip design, chip verification, post silicon validation and software teams.

- Drive strategic technical decision across the different verification teams and the different stages of verification for our Trainium and Inferentia product lines

- Mentor both junior and Senior verification engineers and drive the team’s technical growth as well as individual member’s growth

Requirements: - 6+ years of experience working as verification or chip design engineer

- 2+ years of experience in HW/SW co-design-based testing

- Proven experience developing SW based tests for ML accelerator SOC

- 3+ years experience working on the verification of AI acceleration engines

- Computer architecture and AI acceleration HW architecture knowledge

- Deep understanding of hardware verification methodologies and coverage analysis

- Experience testing on emulation platforms