Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

Saved job description

Annapurna Labs (our organization within Amazon Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Amazon provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries.

Custom SoCs (System on Chip) live at the heart of Amazon Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we’re handling massive scale and rapid integration of emergent technologies. We’re looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs.

Key job responsibilities

Define, develop and deploy innovative STA/EMIR signoff and physical design methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes

Drive Optimizations in CAD flows/methodologies for Timing/EMIR signoff, PPA and TAT improvements

Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability.

Fine tune cloud infrastructure to improve compute and storage utilization for physical design work.

Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.

Be able to independently troubleshoot digital tool flow usage and deploy solutions;

Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments

Create Dashboard and Central reports for project tracking and visualizing QoR/stats

A day in the life

Requirements: - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience

- Bachelor's degree in Electrical Engineering or a related field

- Knowledge of implementing chips with multiple power islands and power gating

- Experience leading or solely developing methodology and scripts for physical synthesis

- Experience low power design techniques

- Experience leading technical initiatives and key deliverables

- Experience with version control systems and CI/CD pipeline implementation